1. Field of the Invention
The present invention relates to a dry etching method suitable for use in a semiconductor device, and particularly to a dry etching method suitable for use in a semiconductor device in which an N type polysilicon gate and a P type polysilicon gate exist in mixed form.
2. Description of the Related Art
The scale-down or miniaturization of a semiconductor element has definitely been put forward at the request of the speeding up of an LSI and a reduction in its power consumption. As to a process for manufacturing a gate electrode in particular, the accuracy of its formation leads to the performance of a transistor, by extension, it is significantly related to the capability of the whole LSI. Therefore, this encounters a confrontation with a strict demand in particular. Simultaneously with an improvement in dimensional accuracy, there has also been a demand for an improvement in driving force of the transistor. In a prior device, the doping of a gate with an impurity has generally been performed on a self-alignment basis upon a source/drain ion implanting process after the patterning formation of the gate.
In this case, only a non-doped polysilicon (Poly-Si) electrode may be etched in a gate patterning process. Since, however, this method is not capable of sufficiently obtaining the driving force of the transistor, a system (hereinafter called “dual gate system”) for doping a gate electrode with an impurity in advance before etching now starts to be adopted. This system will cause a need to take into consideration the type of impurity and a difference in dimension due to impurity density in addition to a difference in dimension due to the loose/dense difference between patterns upon etching.
FIG. 1 shows the result of measurement of dimensions where the dual gate system is adopted. When etching conditions are set such that the dimension of an N type polysilicon gate is controlled constant, the dimension of a P type polysilicon gate greatly changes. When the amount of ion-implantation of an impurity is small, there is little difference in dimension, whereas when phosphor (P) and boron (B) are respectively ion-implanted into the gates by a dose of 5E15 cm−2, a dimensional difference of about 0.037 μm takes place. That is, it is understood that the difference in dimension between two types of different gate regions extends in proportion to a density difference.
When normal two-stage dry etching constituted of, for example, a main step (HBr/O2 flow rate=100/3 sccm, high-frequency power/low-frequency power=250 W/30 W, pressure: 1 Pa and temperature: 60° C.) and an overetching step (HBr/O2/He flow rate=100/2/100 sccm, high-frequency power/low frequency power=250 W/50 W, pressure: 8 Pa and temperature: 60° C.) is performed, end point detection in the main step occurs in an N type polysilicon gate region fast in etching rate. Upon the end point detection, polysilicon in a P type polysilicon gate region still remains. Further, the remaining polysilicon is etched under an overetch condition corresponding to the next overetching step. Therefore, each P type polysilicon gate is assumed to be taper-shaped as shown in FIG. 2. This tendency takes place regardless of the looseness/denseness of patterns.
On the other hand, the technique of flattening an interlayer insulating film by chemical mechanical polishing or the like to ensure a margin by photolithography under a strict design rule with the scale-down of an LSI has been applied to a large number of devices. However, it is understood that since, however, the pressure at each point on a wafer changes because the pattern density is ununiform, the dependence of the pattern density on the amount of polishing occurs in the case of polishing. As a measure taken to cope with such a situation, there has been introduced such a contrivance that dummy patterns are fabricated to reduce the difference in density between the patterns in the wafer.
A polysilicon layer has been used for many kinds of elements such as resistance wiring, a capacitor electrode, etc. as well as a gate electrode of a transistor. The type and density of impurity to be introduced also come in many forms and correspondingly, ion-implantation conditions also vary widely. Depending on the devices, there have been considered various forms such as a case in which a region subjected to ion implantation and a region with no ion implantation exist in mixed form on the same wafer, the use of a non-doped polysilicon gate perfectly unsubjected to ion implantation, etc.
Patent documents 1 through 3:                Japanese Unexamined Patent Publication No. 2000-58511        Japanese Unexamined Patent Publication No. 2000-164732        Japanese Unexamined Patent Publication No. Hei 11(1999)-204506        
As described above, the dual gate type device has a problem in that when the N type polysilicon gate and the P type polysilicon gate are simultaneously dry-etched, it is difficult to control them to the same finished dimension. As a result, a problem has arisen that the miniaturization of the transistor and an improvement in the performance thereof have been impaired.